The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to a semiconductor device having a MIS (Metal Insulator Semiconductor) transistor using a metal silicide electrode and a method of fabricating the same.
To realize high performance of MOSFETs, micropatterning of devices have been sought until today.
Unfortunately, the scaling of gate oxide films is said to be limited in devices on and after the 0.1-μm generation. This is so because the increase in gate leakage current caused by a tunneling current becomes significant as the gate oxide film thickness decreases.
In addition, depletion of the gate electrode is no longer negligible in this generation, so it is presently impossible to freely decrease the effective oxide film thickness.
As a method of avoiding this problem, it is being attempted to increase the dielectric constant of a gate insulating film or to use a metal gate electrode.
The purpose of the former is to increase the physical film thickness and suppress a tunneling current by replacing a gate insulating film with a high-dielectric film.
The purpose of the latter is to prevent depletion of the gate electrode by metallizing it.
Recently, the development of the materials of high-dielectric gate insulating films is being extensively done, and new materials such as HfO2 and La2O3 are reported in learned societies. This produces the competition of decreasing the effective oxide film thickness.
On the other hand, the study of metal gate electrodes is not so extensively done as the development of high-dielectric films. However, as shown in the ITRS 2001 Road Map, in a region where the physical film thickness is less than 1.2 nm, it is presumably difficult to realize a transistor by using an electrode made of the conventional polysilicon.
The influence of depletion of the gate electrode on the effective oxide film thickness is about 0.3 nm. However, to extend the life of silicon-based oxide films to this generation, the development of metal gate electrodes is essential. In particular, the competition of the development of full-silicide electrode processes is advancing because this process is superior in matching with the conventionally used CMOS process.
Unfortunately, in the full-silicide electrode processes, silicide films different in thickness must be separately formed on a diffusion layer and a gate electrode in order to form both a shallow junction and a low-resistance gate electrode.
To protect the device from an oxidizing ambient, the surface of a silicide film must be covered with a silicon nitride film. In the conventional method, an interlayer insulating film structure made of a silicon oxide film on a diffusion layer is sandwiched by silicon nitride films. Therefore, when contact holes are to be simultaneously formed on the diffusion layer and the gate electrode, the etching amount on the gate electrode side excessively increases. In the worst case, etching advances through the gate electrode.
The references disclosing the conventional silicide electrode processes are as follows.    Patent Reference 1: Japanese Patent Laid-Open No. 2000-133705    Patent Reference 2: Japanese Patent Laid-Open No. 2000-353803    Patent Reference 3: Japanese Patent Laid-Open No. 2000-216242    Patent Reference 4: Japanese Patent Laid-Open No. 11-214677    Patent Reference 5: U.S. Pat. No. 6,518,642    Patent Reference 6: U.S. Pat. No. 6,555,450    Patent Reference 7: U.S. Pat. No. 6,586,809